Yannan (Nellie) Wu

I am a senior research engineer at Meta SuperIntelligence Labs (MSL), Fundamental AI Research (FAIR) division. My research is around next-generation hardware-efficient machine learning model architecture design and performance optimizations. Prior to joining Meta, I was a machine learning accelerator modeling engineer at Google, focusing on analytical modeling of next-generation TPUs and Gemini workloads performance analysis.

I obtained my Ph.D. from MIT in computer architecture and systems, advised by Professors Joel Emer and Vivienne Sze. I have extensive research experience modeling and designing energy-efficient hardware accelerators for data and computation-intensive applications (such as deep neural networks), in both academic and industrial settings. My works have led to significant contributions to open-source industrial code bases, publications/tutorials at top-tier conferences (e.g., MICRO, ISCA), and a US patent application.