Publications
HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity
Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer
IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2023.
Accelerating Sparse Tensor Algebra by Overbooking Buffer Occupancy
Fisher Zi Yue Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2023.
LoopTree: Enablilng Exploration of Fused-Layer Dataflow Accelerators
Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Joel S. Emer, Vivienne Sze
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2023..
Sparseloop: An Analytical Approach to Sparse Tensor Accelerator Modeling
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2022.
Architecture-Level Energy Estimation for Heterogeneous Computing Systems
Francis Wang, Yannan Nellie Wu, Matthew Woicik, Vivienne Sze, Joel S. Emer
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2021.
Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2021.
An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs
Yannan Nellie Wu, Vivienne Sze, Joel S. Emer
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2020.
A Systematic Approach for Architecture-Level Energy Estimation of Accelerator Designs
Yannan Nellie Wu
Master Thesis, MIT, Feb. 2020.
Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs
Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2019.
Patents
Pruning And Accelerating Neural Networks With Hierarchical Structured Sparsity
US Patent Application Number: 63/236,629.
Tutorials
Sparse Tensor Accelerators: Abstraction and Modeling
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2021.
Tools for Evaluating Deep Neural Network Accelerator Designs
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2020.
Tools for Evaluating Deep Neural Network Accelerator Designs
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2020.
Tools for Evaluating Deep Neural Network Accelerator Designs
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
IEEE/ACM International Symposium on Microarchitecture (MICRO), Oct. 2019.